1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to the detection of power supply voltage drops in a semiconductor integrated circuit.
2. Description of the Related Art
As semiconductor integrated circuits become ever more densely integrated, the width of their internal power supply lines is reduced, and the resulting increased resistance impedes the supply of power to their internal circuitry. To compound this problem, semiconductor integrated circuits comprise increasingly large numbers of transistors operating at increasingly high speeds, therefore drawing increasing amounts of current, which must be fed through the increased resistance of the power supply lines. This combination of current and resistance can produce significant voltage drops on the power supply lines, and these voltage drops can lead to various types of circuit malfunctions.
A known method of dealing with this problem without sacrificing integration density or operating speed is to monitor the power supply voltage at strategic points within the integrated circuit and take corrective action if a voltage drop is detected. Corrective action might include, for example, boosting the supply voltage, or reducing the clock speed or making other timing adjustments that enable the semiconductor integrated circuit to operate correctly despite the power supply voltage drop.
Japanese Patent Application Publication (JP) No. 2001-332699 places voltage detection cells at specified positions on the power lines of a semiconductor integrated circuit and provides a voltage drop detection circuit that detects voltage drops at these positions. A voltage detection cell is a cell consisting only of a stub leading from the power line to a detection pad. The detection pad is connected by a wiring line to the voltage drop detection circuit, which uses the input voltage received via the wiring line to delay a reference clock signal by a variable amount. A flip-flop clocked by the reference clock signal receives the delayed clock signal as input data and outputs a signal that is high when the delay is small and low when the delay is large. The signal output from the flip-flop is supplied to an external power source to indicate whether or not it is necessary to adjust the power supply voltage.
This voltage drop detection circuit depends on the production of an accurate delay in response to the input voltage. JP 11-8552 describes a slew rate limiter that can produce an accurate delay by supplying the reference clock signal to an inverter connected in series between a pair of current sources controlled by the input voltage, and supplying the output of the inverter to a buffer circuit.
A problem with the semiconductor integrated circuit described in JP 2001-332699 is that the wiring line may be fairly long, because the voltage drop detection circuit is located near a bonding pad at the periphery of the integrated circuit while the voltage detection cell may be located deep in the interior of the integrated circuit. The wiring line therefore has substantial parasitic resistance and capacitance and tends to pick up considerable electrical noise from other parts of the semiconductor integrated circuit en route to the voltage drop detection circuit. These effects make it difficult to detect fluctuations in the power supply voltage accurately, even if the slew-rate limiter described in JP 11-8552 is employed.